US Patent 9135960 Signal receiver circuit

The signal receiver circuit includes a selection signal generator generating first and second selection signals in response to at least one of an electrical open/short state of a fuse and test mode signals, an internal reference voltage generator amplifying an external reference voltage signal after reducing static electricity created by the external reference voltage signal to generate a plurality of internal voltage signals and generating an internal reference voltage signal using the plurality of internal voltage signals in response to the first and second selection signals, and a buffer buffering an internal signal in response to the internal reference voltage signal to generate a control signal for controlling an internal circuit.