Patent attributes
The present disclosure describes techniques and apparatuses for switching between processor cache and random-access memory. In some aspects, the techniques and apparatuses are able to reduce die size of application-specific components by forgoing dedicated random-access memory (RAM). Instead of using dedicated RAM, a memory having a cache configuration is reconfigured to a RAM configuration during operations of the application-specific component and then, when the operations are complete, the memory is configured back to the cache configuration. Because many application-specific components already include memory having the cache configuration, reconfiguring this memory rather than including a dedicated RAM reduces die size for the application component.
