Patent attributes
Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.
