US Patent 9147034 Circuit layout verification method

A method for operating a data processing system to generate a layout for a netlist circuit based on a physical layout of that circuit is disclosed. A schematic of the circuit and an input defining a physical layout of the circuit are received by the data processing system. The schematic includes a plurality of schematic devices, characterized by unique schematic device names. The data processing system generates a graphical representation of the circuit from the physical layout, having one layout device corresponding to each of the plurality of schematic devices, each layout device being characterized by a graphical representation name that is the same as the schematic device name of the corresponding schematic device. First and second netlists are generated from the graphical representation and schematic, respectively. The data processing system generates a report specifying any differences in the first and second netlists.