Patent attributes
An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or more layers of dynamic random-access memory (DRAM) and a system element coupled with the memory stack, the system element including a memory controller for control of the memory stack, and repair logic that is coupled with the memory controller. The repair logic is to hold repair addresses that are identified as failing addresses for defective areas of the memory stack, with the repair logic to receive a memory operation request and implement redundancy repair for an operation address for the request using a repair logic memory to store the repair addresses and data for the repair addresses.
