Patent attributes
A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.
