US Patent 9159672 Through via connected backside embedded circuit features structure and method

A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.