Patent attributes
Backwards compatible architecture for improving the arithmetic capability of existing processing blocks for relatively low cost is disclosed. The architecture includes a processing block on an integrated circuit device. The processing block includes a first, a second, and a third configurable multiplier and a configurable adder network. The processing block also includes a configurable interconnect within the processing block for routing signals between each of the multipliers and the adder network in accordance with a mode of operation. One or more of the processing blocks may be used to perform compute various calculations such as complex number multiplication and/or real number multiplication. The calculations may be performed on input values contain various numbers of bits, such as 36 bit numbers, 54 bit numbers, or 72 bit numbers.
