US Patent 9166844 Receiver with duobinary mode of operation

An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.