US Patent 9208858 Static random access memory with assist circuit

A static random access memory (SRAM) includes a first port word line, a second port word line, a first port bit line and a first port complementary bit line, a second port bit line and second port complementary bit line, and a memory cell having a data node coupled to the first and second port bit lines and a complementary data node coupled to the first and second port complementary bit lines. The first and second port word lines control access to the dual port memory cell. A circuit couples the second port bit line to a high voltage supply node during a write logic high operation to the data node through the first port bit line and couple the second port complementary bit line to the high voltage supply node during a write logic high operation to the complementary data node through the first port complementary bit line.