US Patent 9215107 Dual loop clock and data recovery

A clock and data recovery (CDR) apparatus includes an analog to digital converter configured to sample an input signal according to a sampling clock and provide a digitized signal, a first loop circuit configured to provide a first equalized signal corresponding to the digitized signal, and a slicer configured to provide a data signal based on the first equalized signal. A second loop circuit is configured to provide a second equalized signal corresponding to the digitized signal and adjust the sampling clock according to the second equalized signal. A CDR method includes converting an analog signal into a digitized signal using a sampling clock, providing a first equalized signal using the digitized signal, providing a second equalized signal using the digitized signal, determining the sampling clock using the second equalized signal, and generating a data signal using the first equalized signal.