US Patent 9224476 Semiconductor memory device including a NAND string

According to one embodiment, a semiconductor memory device includes a first NAND string and a second NAND string are connected to a bit line. One of the first and second NAND strings is selected by first to fourth select memory cells. At the write time, data is written in a first memory cell of the first NAND string selected by of the first to fourth select memory cells, then data is written in a second memory cell of the second NAND string selected at the same time as the first memory cell, data is written in a third memory cell adjacent to the first memory cell of the first NAND string and finally data is written in a fourth memory cell of the second NAND string selected at the same time as the third memory cell.