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US Patent 9230973 Methods of fabricating a three-dimensional non-volatile memory device

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9230973
Patent Inventor Names
Jayavel Pachamuthu0
Johann Alsmeier0
Raghuveer S. Makala0
Yao-Sheng Lee0
Date of Patent
January 5, 2016
Patent Application Number
14264262
Date Filed
April 29, 2014
Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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0
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US Patent 12068187 3D semiconductor device and structure with bonding and DRAM memory cells
0
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US Patent 12080743 Multilevel semiconductor device and structure with image sensors and wafer bonding
0
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US Patent 12094892 3D micro display device and structure
0
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
0
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US Patent 12120880 3D semiconductor device and structure with logic and memory
0
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
0
...
Patent Primary Examiner
‌
Cheung Lee
Patent abstract

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

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