US Patent 9232651 Load reduced memory module
Patent 9232651 was granted and assigned to Rambus on January, 2016 by the United States Patent and Trademark Office.
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The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.
US Patent 09232651 Load reduced memory module US Patent 9232651 Load reduced memory module
US Patent 09232651 Load reduced memory module
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