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US Patent 9262359 Method and system for implementing pipeline flip-flops

Patent 9262359 was granted and assigned to Cadence Design Systems on February, 2016 by the United States Patent and Trademark Office.

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Patent attributes

Current Assignee

Cadence Design Systems

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Dennis Huang0

Adrian Aloysius Hendroff0

Anurag Tomar0

David C. Noice0

Scot A. Woodward0

Date of Patent

February 16, 2016

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Patent Application Number

126313760

Date Filed

December 4, 2009

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Patent Citations Received

US Patent 12135928 Constraints and objectives used in synthesis of a network-on-chip (NoC)

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US Patent 11675726 Interconnect repeater planning and implementation flow for abutting designs

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US Patent 11748535 System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

US Patent 11784909 Quality metrics for optimization tasks in generation of a network

US Patent 11838211 System and method to determine optimal path(s) and use load balancing in an interconnect

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US Patent 11836427 Constraints and objectives used in synthesis of a network-on-chip (NoC)

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US Patent 11956127 Incremental topology modification of a network-on-chip

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US Patent 12067335 Automatic configuration of pipeline modules in an electronics system

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Patent Primary Examiner

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Patent abstract

Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.

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