US Patent 9264276 Adaptations for partial response summation node embedded FPGA transceiver

Systems and methods are described that include adaptation circuitry for processing a data signal. The adaptation circuitry may include summation node circuitry for processing an error value associated with the data signal. The adaptation circuitry may also include adaptation engine circuitry, coupled to the summation node circuitry, for controlling the operation of the summation node circuitry.