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US Patent 9276064 Fabricating stacked nanowire, field-effect transistors
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Patent
Date Filed
November 7, 2014
Date of Patent
March 1, 2016
Patent Application Number
14535433
Patent Citations Received
US Patent 12027374 Processes to deposit amorphous-silicon etch protection liner
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US Patent 11715803 Method of forming transistors of different configurations
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US Patent 11777032 Semiconductor devices and methods of manufacturing the same
US Patent 11843000 Semiconductor device
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Patent Inventor Names
Gabriel Padron Wells
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Guillaume Bouche
0
Hui Zang
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9276064
Patent Primary Examiner
Thien F. Tran
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