Patent attributes
A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
