US Patent 9305604 Discrete three-dimensional vertical memory comprising off-die address/data-translator

The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least an A/D-translator die. The 3D-array die comprises a plurality of vertical memory strings. At least an address/data (A/D)-translator for the 3D-array die is located on the A/D-translator die instead of the 3D-array die. The 3D-array die and the A/D-translator die have substantially different back-end-of-line (BEOL) structures.