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US Patent 9305849 Method of making a three dimensional NAND device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 12, 2014
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Date of Patent
April 5, 2016
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Patent Application Number
14539372
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Patent Citations Received
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US Patent 11943928 Method for forming channel hole plug of three-dimensional memory device
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US Patent 11658155 Semiconductor storage device
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US Patent 11716847 Three-dimensional NAND memory device with split gates
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US Patent 11889683 Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
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US Patent 11917823 Channel structures having protruding portions in three-dimensional memory device and method for forming the same
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US Patent 11925019 Channel structures having protruding portions in three-dimensional memory device and method for forming the same
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Patent Inventor Names
George Matamis
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Raghuveer S. Makala
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Rahul Sharangpani
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Sateesh Koka
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Senaka Kanakamedala
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Shigehiro Fujino
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Wei Zhao
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Yanli Zhang
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Masanori Tsutsumi
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
9305849
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Patent Primary Examiner
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Jerome Jackson, Jr.
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