Patent attributes
As disclosed herein, a method for fabricating a nanowire device with improved epitaxy, includes forming a nanowire stack on a substrate, the nanowire stack having one or more sacrificial layers, where the substrate includes a bulk substrate, an oxide layer, and an extremely thin silicon (ETSOI) layer, removing the sacrificial layers, depositing and patterning a gate material over the nanowire stack, the gate material having sidewalls, covering the sidewalls of the gate material with a spacer layer, and epitaxially growing an in-situ doped layer comprised of doped silicon from the ETSOI layer. The ETSOI may have a (100) crystallographic orientation. A pFET source/drain may be epitaxially grown by including an in-situ doped layer of boron doped SiGe. An nFET source/drain may be epitaxially grown by including an in-situ doped layer of phosphorus doped Si:C. A device corresponding to the method is also disclosed herein.