US Patent 9349436 Semiconductor memory and method of making the same

A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line. The VSS conductor and the first word-line extend in a second direction different than the first direction. A third layer comprises a second VSS conductor. The second VSS conductor extends in the first direction. A fourth layer comprises a second word-line. The second word-line extends in the second direction. The first word-line is electrically coupled to the second word-line.