Patent attributes
A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.
