Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Toru Ishikawa0
Keisuke Nomoto0
Date of Patent
June 28, 2016
0Patent Application Number
148039000
Date Filed
July 20, 2015
0Patent Citations Received
Patent Primary Examiner
Patent abstract
The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.
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