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US Patent 9379078 3D die stacking structure with fine pitches

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 7, 2013
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Date of Patent
June 28, 2016
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Patent Application Number
14074186
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Patent Citations Received
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US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
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US Patent RE49987 Multiple plated via arrays of different wire heights on a same substrate
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US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
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US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging
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US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic
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US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging
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US Patent 12075734 Volumetric budget based irrigation control
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US Patent 11764190 3D stacked compute and memory with copper pillars
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US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond
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US Patent 11791233 Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
•••
Patent Inventor Names
Chen-Hua Yu
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Chen-Shien Chen
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Yen-Chang Hu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
9379078
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Patent Primary Examiner
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Laura Menz
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