A resistance variable memory includes a plurality of first wires, a plurality of second wires, a controller, a memory cell array, a second current rectifying element and a second variable resistance element, an access controller, a first contact plug, and a second contact plug. The access controller switches the second variable resistance element to a low resistance state or a high resistance state in accordance with a voltage applied to the memory cell connected in series. The first contact plug is connected to the even-numbered first wire in the second direction from the substrate via the corresponding access controller. The second contact plug is connected to the odd-numbered first wire in the second direction from the substrate via the corresponding access controller.