Patent attributes
A method and apparatuses for securing an integrated circuit (IC) with a self-destruction mechanism are provided. The IC has a tamper detect circuit that will detect unwanted or unauthorized access to the IC. The IC may store configuration and user data in a memory module. The memory module may be an internal or an external non-volatile or volatile memory source. Configuration and user data stored in the memory module is erased when a tamper condition is detected. The IC is powered down after the erase operation is completed. When the IC is powered down, data stored in a static random access memory (SRAM) module in the IC is erased. When the IC is powered up again, the IC will be in a non-operative state as the configuration data has been completely erased.
