US Patent 9407273 Digital delay-locked loop (DLL) training

A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the delay added to the feedback signal to align a leading edge transition in the feedback signal with a leading edge transition in the reference clock signal. The DLL training circuit further provides an inverted feedback signal to the DLL and receives a second delay code value from the DLL that corresponds to the delay added to the inverted feedback signal to align a leading edge transition in the inverted feedback signal with a leading edge transition in the reference clock signal. The DLL selectively adds the delay code corresponding to the temporally smaller of the first delay code value or the second delay code value to the feedback signal to align the feedback signal with the reference clock signal.