Patent attributes
An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.
