US Patent 9412695 Interconnect structures and methods of fabrication

Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.