US Patent 9412828 Aligned gate-all-around structure

A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion.