Patent attributes
The present disclosure provides a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down (PD) device, and a second PD device; a second inverter cross-coupled to the first inverter, the second inverter including a second PU device, a third PD device, and a fourth PD device; first and second pass gate (PG) devices coupled to the first inverter to form a first port; and third and fourth PG devices coupled to the second inverter to form a second port. The first and second PG devices, the first PD device of the first inverter, and the third PD device of the second inverter are configured on a first active region. The third and fourth PG devices, the second PD device of the first inverter, and the fourth PD device of the second inverter are configured on a second active region.