US Patent 9432025 Techniques for reducing skew between clock signals

A clock signal generation circuit generates a first clock signal based on second and third clock signals. The clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals. A skew reduction circuit reduces skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin of the clock signal generation circuit.