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US Patent 9455028 Adaptive negative bit line write assist

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Patent Citations Received
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US Patent 12020746 Memory write assist with reduced switching power
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edited on 1 May, 2024
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Patent Citations Received
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US Patent 11972793 Integrated circuit device including an SRAM portion having end power select circuits
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edited on 10 Apr, 2024
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US Patent 11955171 Integrated circuit device including an SRAM portion having end power select circuits
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Edits on 5 Dec, 2023
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edited on 5 Dec, 2023
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Patent abstract

A memory is provided with a write assist circuit that responds to an indication that a write operation on a modeled memory cell is successful by releasing a negative bit line boost.

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Patent Inventor Names
Rahul Sahu0
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edited on 24 May, 2023
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=094550280
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edited on 24 May, 2023
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US Patent 09455028 Adaptive negative bit line write assist US Patent 9455028 Adaptive negative bit line write assist

Infobox
Patent Number
094550280
Patent Number
94550280
Edits on 25 Sep, 2022
"Entity importer update"
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edited on 25 Sep, 2022
Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
094550280
Date of Patent
September 27, 2016
0
Patent Application Number
148609160
Date Filed
September 22, 2015
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=094550280
Patent Primary Examiner
‌
Han Yang
0
Edits on 6 Jun, 2022
"Entity importer update"
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edited on 6 Jun, 2022
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=09455028
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created this topic on 8 Jan, 2022
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 US Patent 09455028 Adaptive negative bit line write assist

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
09455028
Date of patent
September 27, 2016
Patent application number
14860916
Date Filed
September 22, 2015
Patent primary examiner
‌
Han Yang

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