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US Patent 9459177 Wafer-level testing of optical circuit devices
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Patent
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Date Filed
May 15, 2015
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Date of Patent
October 4, 2016
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Patent Application Number
14713560
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Patent Citations Received
US Patent 11788929 Techniques for wafer level die testing using sacrificial structures
US Patent 12014962 Systems and methods for wafer-level photonic testing
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Patent Inventor Names
Po Dong
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Young-Kai Chen
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
9459177
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Patent Primary Examiner
Tri T Ton
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