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US Patent 9472560 Memory cell and an array of memory cells

Patent 9472560 was granted and assigned to Micron Technology on October, 2016 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Micron Technology
Micron Technology
Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9472560
Patent Inventor Names
Durai Vishak Nirmal Ramaswamy0
Marco Domenico Tiburzi0
Wayne Kinney0
Date of Patent
October 18, 2016
Patent Application Number
14305459
Date Filed
June 16, 2014
Patent Citations Received
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US Patent 11694737 Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects
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US Patent 11696450 Common mode compensation for multi-element non-linear polar material based gain memory bit-cell
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US Patent 11696451 Common mode compensation for non-linear polar material based 1T1C memory bit-cell
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US Patent 11751403 Common mode compensation for 2T1C non-linear polar material based memory bit-cell
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US Patent 11758708 Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
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US Patent 11765908 Memory device fabrication through wafer bonding
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US Patent 11770936 Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
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US Patent 11769543 Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell
...
Patent Primary Examiner
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Han Yang
Patent abstract

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

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