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US Patent 9501392 Management of a non-volatile memory module
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Patent
Date Filed
May 20, 2014
Date of Patent
November 22, 2016
Patent Application Number
14282204
Patent Citations Received
US Patent 12124383 Systems and methods for cache optimization
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US Patent 12066975 Cache structure and utilization
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US Patent 12079155 Graphics processor operation scheduling for deterministic latency
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US Patent 12093210 Compression techniques
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US Patent 11714553 Namespaces allocation in non-volatile memory devices
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US Patent 11842423 Dot product operations on sparse matrix elements
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US Patent 11928332 Namespace size adjustment in non-volatile memory devices
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US Patent 11934342 Assistance for hardware prefetch in cache access
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US Patent 11954062 Dynamic memory reconfiguration
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US Patent 11954063 Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
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•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9501392
Patent Primary Examiner
David X Yi
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