US Patent 9508397 Non-volatile memory (NVM) with endurance control

An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.