US Patent 9515138 Structure and method to minimize junction capacitance in nano sheets

A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.