A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell. The sense amplifier connects to the bit line. The register holds write data, and a write voltage. The controller outputs a busy signal. The controller causes the register to hold the write data and the write voltage upon receiving the first command, and resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command.