Patent attributes
A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer comprising a first III-Nitride material, a barrier layer comprising a second III-Nitride material, a pair of ohmic electrodes disposed in ohmic recesses etched into the barrier layer, a gate electrode disposed in a gate recess etched into the barrier layer, and a filler element. The gate electrode is stepped to form a bottom stem and at least one bottom step within the gate recess. The filler element, comprising an insulating material, is disposed at least below the bottom step of the gate electrode within the gate recess. Also described are methods for fabricating such semiconductor structures. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
