Patent attributes
An apparatus is provided that includes a two-wire loop having first and second conductors that connect a monitoring system with a plurality of addressable sensors and alarm devices of the monitoring system, the two-wire loop having first and second ends connected to the monitoring system, a memory that contains first respective resistance values of the first and second conductors and second respective resistance values between the first and second ends and each of the plurality of addressable sensors and alarm devices, and a processor that detects a fault in the two-wire loop by measuring third resistance values from opposing ones of the first and second ends of the two-wire loop during a scan of the plurality of addressable sensors and alarm devices and compares the third resistance values with corresponding ones of the first and second respective resistance values in the memory.