Patent attributes
The present disclosure provides methods for removing gate electrode residuals from a gate structure after a gate electrode patterning process. In one example, a method for forming high aspect ratio features in a gate electrode layer in a gate structure includes performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate, selectively forming a treated residual in the gate structure on the substrate with some untreated regions nearby in the gate structure, and performing a remote plasma residual removal process to remove the treated residual from the substrate.