Patent attributes
A memory device includes an array of programmable resistance memory cells, a differential amplifier coupled to the array, and current circuitry providing a program current to the bit line. The differential amplifier senses a voltage difference between a first voltage on a bit line coupled to a memory cell and a reference voltage, and provides a feedback signal in response to the voltage difference. Control circuitry is coupled to the array and the differential amplifier, and configured to execute a program operation to change the memory cell in a first resistance state to a second resistance state, including selecting a voltage level for the reference voltage which correlates with the second resistance state, turning on the current circuitry to apply a program pulse of program current to the memory cell, and enabling the differential amplifier, where the current circuitry turns off the program current in response to the feedback signal.
