Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
May 23, 2017
Patent Application Number
14307011
Date Filed
June 17, 2014
Patent Citations Received
Patent Primary Examiner
Patent abstract
Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.