Patent attributes
An array substrate having a thin film transistor with an oxide semiconductor layer, wherein the thin film transistor is in a device area of a pixel region; the substrate comprising a light-shielding pattern on the array substrate in the device area; an auxiliary line connected to a light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer on the light-shielding pattern and a surface of the array substrate, wherein the oxide semiconductor layer is on the buffer layer and the light-shielding pattern; an inter-insulating layer on the buffer layer, wherein the oxide semiconductor layer includes an active portion located entirely on the light-shielding pattern and having a channel formed thereon, and conductive portions located on sides of the active portion.
