Patent attributes
A packaged chip assembly with a semiconductor substrate, a semiconductor device integrally formed on or in the substrate's top surface, and first bond pads at the substrate's top surface electrically coupled to the semiconductor device. A second substrate includes a first aperture and one or more second apertures extending therethrough, second and third bond pads at the second substrate's top and bottom surfaces, respectively, and conductors electrically coupled to the second and third bond pads. The semiconductor substrate's top surface is secured to the second substrate's bottom surface such that the semiconductor device is aligned with the first aperture, and each of the first bond pads is aligned with one of the second apertures. A plurality of wires are each electrically connected between one of the first bond pads and one of the second bond pads and each passing through one of the one or more second apertures.
