US Patent 9710651 Secure processor for SoC initialization

An embedded system includes an interface to an external peripheral device storing secure boot code and a secure boot controller. The secure boot controller includes a secure central processing unit (CPU) having a processor core, a random access memory (RAM) coupled to the processor core, and a read only memory (ROM) coupled to the processor core. The ROM stores initialization firmware configured to manipulate the processor core to initiate transfer of a copy of the secure boot code from the external peripheral device to the RAM and to authenticate the secure boot code. The processor core further is to execute the secure boot code from the RAM to initialize the embedded system. After initialization of the embedded system is completed, the secure CPU can be repurposed to execute application code that has been stored to the RAM after initialization, the application code representing an independent software function.