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US Patent 9711529 3D NAND device and fabrication method thereof
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Patent
Date Filed
May 3, 2016
Date of Patent
July 18, 2017
Patent Application Number
15144901
Patent Citations Received
US Patent 11749344 Three-dimensional vertical nor flash thin-film transistor strings
US Patent 11751391 Methods for fabricating a 3-dimensional memory structure of nor memory strings
US Patent 11751392 Fabrication method for a 3-dimensional NOR memory array
US Patent 12002523 Memory circuit, system and method for rapid retrieval of data sets
0
US Patent 11792989 Word line structure of three-dimensional memory device
US Patent 11839086 3-dimensional memory string array of thin-film ferroelectric transistors
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US Patent 11844204 Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
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US Patent 11915768 Memory circuit, system and method for rapid retrieval of data sets
0
US Patent 11842777 Methods for reducing disturb errors by refreshing data alongside programming or erase operations
0
US Patent 11937424 Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same
0
•••
Patent Inventor Names
Huayong Hu
0
Lei Ye
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9711529
Patent Primary Examiner
Stephen W Smoot
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