Patent attributes
Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.